1. Field of the Invention
The present invention generally relates to the design of processors within computer systems. More specifically, the present invention relates to a method and an apparatus for handling fetch requests that return out-of-order at an instruction fetch unit in a processor.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in processor clock speeds. These increasing clock speeds have significantly increased processor performance. However, as clocks speeds continue to increase, it is becoming progressively harder to fetch instructions quickly enough to keep pace with increasing instruction-execution rates. To deal with this problem, some processors are beginning to support multiple outstanding fetch requests to fetch instruction cache lines. This enables multiple fetch requests to be processed in parallel, which can greatly increase the rate at which instructions are fetched. However, the multiple outstanding fetch requests can potentially return out-of-order. Providing mechanisms to handle such out-of-order returns can greatly complicate the design of the instruction fetch unit (IFU). Furthermore, if such mechanisms are not designed properly, the actual number of outstanding fetch requests will be reduced in some situations, which can adversely affect processor performance.
Hence, what is needed is method and an apparatus that efficiently handles fetch requests that return out-of-order without the above-described problems.